"Our customers are finding that the dramatic improvements we have made in place and route runtimes have shifted the product development bottleneck to design verification," said Rich Sevcik, senior vice president of FPGA Products at Xilinx. "In anticipation of this new challenge, we have emphasized improving the verification process for Xilinx designs. Our new hierarchical netlists make HDL simulation and formal verification using our partner's tools fast and intuitive. Ultimately this benefits our customers by helping them better manage their product development costs."

Improved visibility accelerates verification and debug

The Xilinx exclusive technology produces timing netlists that retain the hierarchical structure, logic, and signals of the original source design. The traditional approach to timing simulation of programmable logic designs rely on the generation of a timing netlist that reflects the physical implementation of the design, paying little or no regard to the structure of the original design. This physical-view of the design often makes it difficult to trace the cause of a design bug back to its source, as the physical view frequently contains a mixture of user and machine generated signals and structures.

Xilinx customers will benefit from faster verification and debug cycles because of their intimate knowledge of the timing netlist being simulated. Further, using this technique with formal verification products results in faster and more efficient equivalency checking, as the model under test has the same structure as the "golden" reference design.

Hierarchical structure strengthens advantages of incremental design

Xilinx hierarchical netlists also work hand-in-hand with Xilinx unique incremental design capabilities. Xilinx incremental design works by preserving the physical implementation (logic structure, placement and routing) of unchanged portions of a design, guaranteeing the performance of design blocks that haven't changed. The creation of simulation netlists that retain this same design structure means Xilinx customers can focus their verification and debugging efforts on only those areas of their design that have changed as a result of the recent design revision. This results in faster verification times, and overall design cycles, and is a characteristic that is unique to the Xilinx programmable logic design flow. Engineers considering other programmable logic solutions have to verify the design as a monolith, resulting in longer simulation or formal verification runtimes, and less efficient use of an their time.

Partnering for success

Xilinx hierarchical timing netlists have been optimized to work with HDL simulation and formal verification tools from leading third party EDA vendors. Designers can leverage verification products available from the industry's leading providers, including: Cadence's NCSim, Model Technology's ModelSim, Synopsys' Formality and VCS, and Verplex's Conformal LEC. To learn more about what our partners are saying about Xilinx hierarchical netlists, visit www.xilinx.com/netlists.

About Xilinx ISE version 5.1i

With ISE 5.1i, Xilinx is delivering "ASIC-strength" design tools to exploit the power of Virtex-II Pro(TM) silicon, ranging in device densities from 40,000 to more than eight million system gates. Designers are benefiting from a 2X improvement in compile times (an increase from 100,000 to 200,000 gate/min) and a 40 percent gain in device speeds over last year's software release. With an installed base of more than 150,000 design seats, and more than 50 percent market segment share in the PLD industry, Xilinx ISE is widely regarded as the de facto standard methodology for programmable logic design. To learn more about ISE visit the Xilinx design Tools Center at www.xilinx.com/ise. ISE supports the design, synthesis, implementation, and verification of all Xilinx leading programmable logic devices, including Spartan®-II, Spartan-IIE, Virtex®, Virtex-E, Virtex-II(TM), Virtex-II Pro(TM), and all CoolRunner® series devices.

About Xilinx

Xilinx, Inc. is the worldwide leader of programmable logic and programmable system solutions. Additional information about Xilinx is available at www.xilinx.com.

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